Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-27. Bit Descriptions – Device Status Register
BIT FIELD NAME ACCESS DESCRIPTION
15:6 RSVD r Reserved. When read, these bits return zeros.
Transaction PENDING. This bit is set when the XIO3130 has issued a non-posted transaction
5 PEND ru
that has not been completed yet.
AUX power detected. This bit indicates that AUX power is present. This bit is a direct reflection
of the AUX_PRSNT bit in the Global Chip Control register and has the same default value.
4 APD ru
0 – No AUX power detected.
1 – AUX power detected.
Unsupported request detected. This bit is asserted when a request is received that results in
3 URD rcu sending a completion with an Unsupported Request status). Errors are logged in this bit
regardless of whether error reporting is enabled in the Device Control register.
Fatal error detected. This bit is set by the XIO3130 when a fatal error is detected. Errors are
2 FED rcu
logged in this bit regardless of whether error reporting is enabled in the Device Control register.
Nonfatal error detected. This bit is set by the XIO3130 when a nonfatal error is detected. Errors
1 NFED rcu are logged in this bit regardless of whether error reporting is enabled in the Device Control
register.
Correctable error detected. This bit is set by the XIO3130 when a correctable error is detected.
0 CED rcu Errors are logged in this bit regardless of whether error reporting is enabled in the Device
Control register.
4.2.52 Link Capabilities Register
The Link Capabilities register indicates the link-specific capabilities of the device.
PCI register offset: 9Ch
Register type: Read only
Default value: 000X XX11h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 y y
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE y z z z x 1 0 0 0 0 0 1 0 0 0 1
Table 4-28. Bit Descriptions – Link Capabilities Register
BIT FIELD NAME ACCESS DESCRIPTION
Port number. This field indicates the port number for the PCI Express link. This field is
31:24 PORT_NUM r
read-only zero.
23:19 RSVD r Reserved. When read, these bits return zeros.
Clock power management. This field is read-only 1b, which indicates that CLKREQ is
18 CLK_PM r
supported on the upstream port.
L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the
L0 state. This field is a direct reflection of the Upstream Port Link PM Latency register
17:15 L1_LATENCY r L1_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present). The
default value of this field, yyy, is the same as the default value of the Link PM Latency
register L1_EXIT_LAT field.
L0s exit latency. This field indicates the time that required to transition from the L0s state to
the L0 state. This field is a direct reflection of the Upstream Port Link PM Latency register
14:12 L0S_LATENCY r L0S_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present).
The default value of this field, zzz, is the same as the default value of the Link PM Latency
register L0S_EXIT_LAT field.
Active state link PM support. This field reads either 01b or 11b, which indicates that the
device supports L0s and may or may not support ASPM-based L1 for Active State Link PM.
11:10 ASLPMS r
ASPM-based L1 support is controlled by the ASPM_L1_EN field in the Global Chip Control
register.
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 57
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