Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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4.2.47 Next-Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the

XIO3130. This register reads 00h, which indicates that no additional capabilities are supported.

PCI register offset: 91h

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.2.48 PCI Express Capabilities Register

This register indicates the capabilities of the upstream port of the XIO3130 related to PCI Express.

PCI register offset: 92h

Default value: 0051h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1

Table 4-24. Bit Descriptions – PCI Express Capabilities Register

BIT FIELD NAME ACCESS DESCRIPTION

15:14 RSVD r Reserved. When read, these bits return zeros.

Interrupt message number. This field is used for MSI support and is implemented as read-only

13:9 INT_NUM r

zero in the XIO3130.

Slot implemented. This bit is invalid for the upstream port on the XIO3130 and is read-only

8 SLOT r

zero.

Device/Port type. This read-only field returns 0101b, which indicates that the device is an

7:4 DEV_TYPE r

upstream port of a PCI Express XIO3130.

Capability version. This field returns 0001b, which indicates revision 1 of the PCI Express

3:0 VERSION r

capability.

4.2.49 Device Capabilities Register

The Device Capabilities register indicates the device-specific capabilities of the XIO3130.

PCI register offset: 94h

Default value: 0000 8001h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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Product Folder Link(s): XIO3130