Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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Table 4-22. Bit Descriptions – MSI Message Address Register

BIT FIELD NAME ACCESS DESCRIPTION

31:2 ADDRESS rw System Specified Message Address.

1:0 RSVD r Reserved. When read, these bits return zeros.

4.2.40 MSI Message Upper Address Register

This register contains the upper 32 bits of the address that a MSI message shall be written to when an

interrupt is to be signaled. If this register is 0000 0000h, 32-bit addressing is used; otherwise, 64-bit

addressing is used.

PCI register offset: 78h

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCI register offset: 56h

Default value: 00h

4.2.41 MSI Message Data Register

This register contains the data that software programmed the device to send when it sends a MSI

message.

PCI register offset: 7Ch

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-23. Bit Descriptions – MSI Data Register

BIT FIELD NAME ACCESS DESCRIPTION

System-specific message. This field contains the portion of the message that the XIO3130 can

15:4 MSG rw

never modify.

Message number. This portion of the message field may be modified to contain the message

3:0 MSG_NUM rw number if multiple messages are enabled. Since the XIO3130 only generates one MSI type,

these bits are not modified by XIO3130 hardware.

4.2.42 Capability ID Register

This read-only register identifies the linked list item as the register for Subsystem ID and Subsystem