Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
4.2.34 Power Management Bridge Support Extension Register
This read-only register is used to indicate to host software the state of the secondary bus when the
XIO3130 is placed in D3.
PCI register offset: 56h
Register type: Read only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4-20. Bit Descriptions – PM Bridge Support Extension Register
BIT FIELD NAME ACCESS DESCRIPTION
Bus power/Clock control enable. This bit is read-only zero. This bit does not apply to PCI
7 BPCC r
Express.
6 BSTATE r B2/B3 support. This bit is read-only zero. This bit does not apply to PCI Express.
5:0 RSVD r Reserved. When read, these bits return zeros.
4.2.35 Power Management Data Register
This read-only register is not applicable to the XIO3130 and returns 00h when read.
PCI register offset: 57h
Register type: Read only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.2.36 MSI Capability ID Register
This read-only register identifies the linked list item as the register for Message Signaled Interrupts (MSI)
Capabilities. The register returns 05h when read.
PCI register offset: 70h
Register type: Read only
Default value: 05h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 0 1
4.2.37 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130. This register reads 80h, which points to the Subsystem ID and Subsystem Vendor ID
Capabilities registers.
PCI register offset: 71h
Register type: Read only
Default value: 80h
50 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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