Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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Table 4-17. Bit Descriptions – Bridge Control Register (continued)

BIT FIELD NAME ACCESS DESCRIPTION

Parity error response enable. It is assumed that the relevant error checking is unnecessary for the

0 PERR_EN rw

XIO3130’s internal PCI bus; therefore, setting this bit has no effect.

4.2.30 Capability ID Register

This read-only register identifies the linked list item as the register for PCI power management. The

PCI register offset: 50h

Default value: 01h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1

4.2.31 Next-Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the

XIO3130. This register reads 70h, which points to the MSI Capabilities registers.

PCI register offset: 51h

Default value: 70h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 1 1 0 0 0 0

4.2.32 Power Management Capabilities Register

This register indicates the capabilities of the XIO3130 related to PCI power management.

PCI register offset: 52h

Default value: XX03h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE y 1 1 x 1 1 x 0 0 0 0 0 0 0 1 1

Table 4-18. Bit Descriptions – Power Management Capabilities Register

BIT FIELD NAME ACCESS DESCRIPTION

PME support. This five-bit field indicates the power states from which the (upstream) port may

assert PME. These five bits return a value of 5’by11x1, indicating that the XIO3130 can assert

PME from D0, D2, D3hot, maybe D3cold (i.e., depending on y), and maybe D1 (i.e., depending

15:11 PME_SUPPORT r

on x). The bit defining this for D3cold (i.e., y) is controlled by the AUX_PRSNT bit in the Global

Chip Control register. The bit defining this for D1 (i.e., x) is controlled by the D1_SUPPORT bit in

the Global Switch Control register.

D2 device power state support. This bit returns a 1 when read, which indicates that the function

10 D2_SUPPORT r

supports the D2 device power state.

D1 device power state support. This bit indicates whether the function supports the D1 device

power state. This bit is controlled by the D1_SUPPORT bit in the Global Switch Control register.

9 D1_SUPPORT r

The default value x refers to whatever the default value is for the D1_SUPPORT bit in the Global

Switch Control register.

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