Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-17. Bit Descriptions – Bridge Control Register
BIT FIELD NAME ACCESS DESCRIPTION
15:12 RSVD r Reserved. When read, these bits return zeros.
11 DTSERR r Discard timer SERR enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
10 DTSTATUS r Discard timer status. This bit is hardwired to zero. This bit does not apply to PCI Express.
9 SEC_DT r Secondary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
8 PRI_DEC r Primary discard timer. This bit is hardwired to zero. This bit does not apply to PCI Express.
7 FBB_EN r Fast back-to-back enable. This bit is hardwired to zero. This bit does not apply to PCI Express.
Secondary bus reset. This bit is set when software wishes to reset all devices downstream of the
XIO3130. Setting this bit causes all of the downstream ports to be reset, and all of the downstream
ports to send a reset via a training sequence.
6 SRST rw
0 – Downstream ports not in Reset state.
1 – Downstream ports in Reset state.
5 MAM r Master abort mode. This bit is hardwired to zero. This bit does not apply to PCI Express.
VGA 16-bit decode. This bit enables the XIO3130 to provide full 16-bit decoding for VGA I/O
addresses. This bit only has meaning if the VGA enable bit is set.
4 VGA16 rw
0 – Ignore address bits [15:10] when decoding VGA I/O addresses.
1 – Decode address bits [15:10] when decoding VGA I/O addresses.
VGA enable. This bit modifies the response by the XIO3130 to VGA-compatible addresses. If this
bit is set, the XIO3130 positively decodes and forwards the following accesses on the primary
interface to the secondary interface (and, conversely, blocks the forwarding of these addresses
from the secondary to primary interface):
• Memory accesses in the range 000A 0000h to 000BFFFFh
• I/O addresses in the first 64 KB of the I/O address space (Address bits [31:16] are 0000h)
and where address bits [9:0] is in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of
ISA address aliases – Address bits [15:10] may possess any value and is not used in the
decoding).
If the VGA Enable bit is set, forwarding of VGA addresses is independent of the value of the ISA
3 VGA rw
Enable bit (located in the Bridge Control register), the I/O address range and memory address
ranges defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the
Pre-fetchable Memory Base and Limit registers of the bridge. The forwarding of VGA addresses is
qualified by the I/O Enable and Memory Enable bits in the Command register.
0 – Do not forward VGA-compatible memory and I/O addresses from the primary to secondary
interface (addresses defined above) unless they are enabled for forwarding by the defined
I/O and memory address ranges.
1 – Forward VGA-compatible memory and I/O addresses (addresses defined above) from the
primary interface to the secondary interface (if the I/O Enable and Memory Enable bits are
set) independent of the I/O and memory address ranges and independent of the ISA
Enable bit.
ISA enable. This bit modifies the response by the XIO3130 to ISA I/O addresses. This bit applies
only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first
64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge blocks
any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each
1 KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they
address the last 768 bytes in each 1K block.
2 ISA rw
0 – Forward downstream all I/O addresses in the address range defined by the I/O Base and
I/O Limit registers.
1 – Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O
Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1
KB block).
SERR enable. This bit controls forwarding of system error events upstream from the secondary
interface to the primary interface. The XIO3130 forwards system error events when:
• This bit is set.
• The SERR enable bit in the upstream port command register is set.
1 SERR_EN rw
• SERR is asserted on the secondary interface.
0 – Disable the forwarding of system error events.
1 – Enable the forwarding of system error events.
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