Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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4.2.26 Capabilities Pointer Register

This read-only register provides a pointer into the PCI configuration header where the PCI power

management block resides. Since the PCI power management registers begin at 50h, this register is

hardwired to 50h.

PCI register offset: 34h

Default value: 50h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 1 0 0 0 0

4.2.27 Interrupt Line Register

This read/write register, which is programmed by the system, indicates to the software which interrupt line

the XIO3130 has assigned to it. The default value of this register is FFh, which indicates that an interrupt

line has not yet been assigned to the function. Since the XIO3130 does not generate interrupts internally,

this register is essentially a scratch-pad register; it has no effect on the XIO3130 itself.

PCI register offset: 3Ch

Default value: FFh

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 1 1 1 1 1 1 1 1

4.2.28 Interrupt Pin Register

The Interrupt Pin register is read-only 00h, which indicates that the XIO3130 upstream port does not

generate interrupts. The value of this register has no effect on forwarding interrupts from the downstream

ports to the upstream port.

PCI register offset: 3Dh

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.2.29 Bridge Control Register

The Bridge Control register provides extensions to the Command register that are specific to a bridge.

PCI register offset: 3Eh

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Product Folder Link(s): XIO3130