Specifications

XIO3130

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SLLS693F–MAY 2007–REVISED JANUARY 2010

4.2.23 Pre-fetchable Limit Upper 32 Bits Register

This read/write register specifies the upper 32 bits of the Pre-fetchable Memory Limit register.

PCI register offset: 2Ch

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-14. Bit Descriptions – Pre-fetchable Limit Upper 32 Bits Register

FIELD

BIT ACCESS DESCRIPTION

NAME

Pre-fetchable memory limit upper 32 bits. This field defines the upper 32 bits of the top address of the

PRELIMI

31:0 rw pre-fetchable memory address range used to determine when to forward memory transactions

downstream.

4.2.24 I/O Base Upper 16 Bits Register

This read/write register specifies the upper 16 bits of the I/O Base register.

PCI register offset: 30h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-15. Bit Descriptions – I/O Base Upper 16 Bits Register

BIT FIELD NAME ACCESS DESCRIPTION

I/O base upper 16 bits. This field defines the upper 16 bits of the bottom address of the I/O

15:0 IOBASE rw

address range that is used to determine when to forward I/O transactions downstream.

4.2.25 I/O Limit Upper 16 Bits Register

This read/write register specifies the upper 16 bits of the I/O Limit register.

PCI register offset: 32h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-16. Bit Descriptions – I/O Limit Upper 16 Bits Register

BIT FIELD NAME ACCESS DESCRIPTION

I/O limit upper 16 bits. This field defines the upper 16 bits of the top address of the I/O address

15:0 IOLIMIT rw

range used to determine when to forward I/O transactions downstream.

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