Specifications

XIO3130

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SLLS693F–MAY 2007–REVISED JANUARY 2010

4.2.18 Memory Base Register

This read/write register specifies the lower limit of the memory addresses that the XIO3130 forwards

downstream.

PCI register offset: 20h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-9. Bit Descriptions – Memory Base Register

BIT FIELD NAME ACCESS DESCRIPTION

Memory base. This field defines the bottom address of the memory address range used to

15:4 MEMBASE rw determine when to forward memory transactions from one interface to the other. These bits

correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 0.

3:0 RSVD r Reserved. When read, these bits return zeros.

4.2.19 Memory Limit Register

This read/write register specifies the upper limit of the memory addresses that the XIO3130 forwards

downstream.

PCI register offset: 22h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Table 4-10. Bit Descriptions – Memory Limit Register

BIT FIELD NAME ACCESS DESCRIPTION

Memory limit. This field defines the top address of the memory address range used to determine

15:4 MEMLIMIT rw when to forward memory transactions from one interface to the other. These bits correspond to

address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.

3:0 RSVD r Reserved. When read, these bits return zeros.

4.2.20 Pre-fetchable Memory Base Register

This read/write register specifies the lower limit of the pre-fetchable memory addresses that the XIO3130

forwards downstream.

PCI register offset: 24h

Default value: 0001h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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