Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
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4.2.16 I/O Limit Register
This read/write register specifies the upper limit of the I/O addresses that the XIO3130 forwards
downstream.
PCI register offset: 1Dh
Register type: Read/Write; Read Only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
Table 4-7. Bit Descriptions – I/O Limit Register
BIT FIELD NAME ACCESS DESCRIPTION
I/O limit. These bits define the top address of the I/O address range used to determine when to
forward I/O transactions from one interface to the other. These bits correspond to address bits
7:4 IOLIMIT rw [15:12] in the I/O address. The lower 12 I/O address bits are assumed to be FFFh. The 16 bits
corresponding to address bits [31:16] of the I/O address are defined in the I/O Limit Upper 16 Bits
register.
3:0 IOTYPE r I/O type. This field is read-only 01h, indicating that the XIO3130 supports 32-bit I/O addressing.
4.2.17 Secondary Status Register
The Secondary Status register provides information about the XIO3130’s internal PCI bus between the
upstream port and the downstream ports.
PCI register offset: 1Eh
Register type: Read only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-8. Bit Descriptions – Secondary Status Register
BIT FIELD NAME ACCESS DESCRIPTION
Detected parity error. This bit is hardwired to zero. It is assumed that the relevant error checking
15 PAR_ERR r
is unnecessary for the XIO3130’s internal PCI bus.
Received system error. This bit is hardwired to zero. It is assumed that the relevant error
14 SYS_ERR r
checking is unnecessary for the XIO3130’s internal PCI bus.
Received master abort. This bit is hardwired to zero. It is assumed that the relevant error
13 MABORT r
checking is unnecessary for the XIO3130’s internal PCI bus.
Received target abort. This bit is hardwired to zero. It is assumed that the relevant error checking
12 TABORT_REC r
is unnecessary for the XIO3130’s internal PCI bus.
Signaled target abort. This bit is hardwired to zero. It is assumed that the relevant error checking
11 TABORT_SIG r
is unnecessary for the XIO3130’s internal PCI bus.
10:9 PCI_SPEED r DEVSEL timing. These bits are hardwired to 00. These bits do not apply to PCI Express.
Master data parity error. This bit is hardwired to zero. It is assumed that the relevant error
8 DATAPAR r
checking is unnecessary for the XIO3130’s internal PCI bus.
7 FBB_CAP r Fast back-to-back capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
6 RSVD r Reserved. When read, this bit returns zero.
5 66MHZ r 66 MHz capable. This bit is hardwired to zero. This bit does not apply to PCI Express.
4:0 RSVD r Reserved. When read, these bits return zeros.
42 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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