Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
4.2.13 Subordinate Bus Number
This register specifies the bus number of the highest number PCI bus segment that is downstream of the
XIO3130’s upstream port. The XIO3130 uses this register to determine how to respond to a Type 1
configuration transaction.
PCI register offset: 1Ah
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.2.14 Secondary Latency Timer Register
This register does not apply to PCI-Express. It is hardwired to zero.
PCI register offset: 1Bh
Register type: Read Only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.2.15 I/O Base Register
This read/write register specifies the lower limit of the I/O addresses that the XIO3130 forwards
downstream.
PCI register offset: 1Ch
Register type: Read/Write; Read Only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
Table 4-6. Bit Descriptions – I/O Base Register
BIT FIELD NAME ACCESS DESCRIPTION
7:4 IOBASE rw I/O base. These bits define the bottom address of the I/O address range that is used to determine
when to forward I/O transactions from one interface to the other. These bits correspond to address
bits [15:12] in the I/O address. The lower 12 I/O address bits are assumed to be 0. The 16 bits
corresponding to address bits [31:16] of the I/O address are defined in the I/O Base Upper 16 Bits
register.
3:0 IOTYPE r I/O type. This field is read-only 01h, indicating that the XIO3130 supports 32-bit I/O addressing.
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