Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
4.2.9 Header Type Register
This read-only register indicates that this function has a type one PCI header. Bit seven of this register is a
zero, indicating that the upstream port is a single device.
PCI register offset: 0Eh
Register type: Read Only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
4.2.10 BIST Register
Since the XIO3130 does not support a built-in self test (BIST), this read-only register returns the value of
00h when read.
PCI register offset: 0Fh
Register type: Read Only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.2.11 Primary Bus Number
This read/write register specifies the bus number of the PCI bus segment to which the upstream PCI
Express interface is connected.
PCI register offset: 18h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.2.12 Secondary Bus Number
This read/write register specifies the bus number of the PCI bus segment for the XIO3130’s internal PCI
bus. The XIO3130 uses this register to determine how to respond to a Type 1 configuration transaction.
PCI register offset: 19h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
40 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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