Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
4.2.62 GPIO B Control Register ...................................................................................... 66
4.2.63 GPIO C Control Register ...................................................................................... 68
4.2.64 GPIO D Control Register ...................................................................................... 70
4.2.65 GPIO Data Register ............................................................................................ 72
4.2.66 TI Proprietary Register ......................................................................................... 75
4.2.67 TI Proprietary Register ......................................................................................... 75
4.2.68 TI Proprietary Register ......................................................................................... 75
4.2.69 TI Proprietary Register ......................................................................................... 76
4.2.70 TI Proprietary Register ......................................................................................... 76
4.2.71 TI Proprietary Register ......................................................................................... 76
4.2.72 Subsystem Access Register .................................................................................. 77
4.2.73 General Control Register ...................................................................................... 77
4.2.74 Downstream Ports Link PM Latency Register .............................................................. 78
4.2.75 Global Switch Control Register ............................................................................... 79
4.2.76 Advanced Error Reporting Capability ID Register .......................................................... 80
4.2.77 Next Capability Offset/Capability Version Register ........................................................ 80
4.2.78 Uncorrectable Error Status Register ......................................................................... 80
4.2.79 Uncorrectable Error Mask Register .......................................................................... 81
4.2.80 Uncorrectable Error Severity Register ....................................................................... 82
4.2.81 Correctable Error Status Register ............................................................................ 83
4.2.82 Correctable Error Mask Register ............................................................................. 84
4.2.83 Advanced Error Capabilities and Control Register ......................................................... 85
4.2.84 Header Log Register ........................................................................................... 86
4.3 PCI Express Downstream Port Registers .............................................................................. 87
4.3.1 PCI Configuration Space (Downstream Port) Register Map .............................................. 87
4.3.2 Vendor ID Register ............................................................................................. 88
4.3.3 Device ID Register ............................................................................................. 88
4.3.4 Command Register ............................................................................................. 88
4.3.5 Status Register .................................................................................................. 89
4.3.6 Class Code and Revision ID Register ....................................................................... 90
4.3.7 Cache Line Size Register ..................................................................................... 91
4.3.8 Primary Latency Timer Register .............................................................................. 91
4.3.9 Header Type Register .......................................................................................... 91
4.3.10 BIST Register ................................................................................................... 91
4.3.11 Primary Bus Number ........................................................................................... 92
4.3.12 Secondary Bus Number ....................................................................................... 92
4.3.13 Subordinate Bus Number ...................................................................................... 92
4.3.14 Secondary Latency Timer Register .......................................................................... 92
4.3.15 I/O Base Register ............................................................................................... 93
4.3.16 I/O Limit Register ............................................................................................... 93
4.3.17 Secondary Status Register .................................................................................... 93
4.3.18 Memory Base Register ......................................................................................... 94
4.3.19 Memory Limit Register ......................................................................................... 95
4.3.20 Pre-fetchable Memory Base Register ........................................................................ 95
4.3.21 Pre-fetchable Memory Limit Register ........................................................................ 95
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