Specifications

XIO3130

www.ti.com

SLLS693F–MAY 2007–REVISED JANUARY 2010

4.2.6 Class Code and Revision ID Register

This read-only register categorizes the Base Class, Sub Class, and Programming Interface of the

XIO3130. The Base Class is 06h, identifying the device as bridge device. The Sub Class is 04h,

identifying the function as a PCI-to-PCI bridge, and the Programming Interface is 00h. Also, the TI chip

revision is indicated in the lower byte (02h).

PCI register offset: 08h

Default value: 0604 0002h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Table 4-5. Bit Descriptions – Class Code and Revision ID Register

BIT FIELD NAME ACCESS DESCRIPTION

31:24 BASECLASS r Base Class. This field returns 06h when read, which classifies the function as a Bridge device.

Sub Class. This field returns 04h when read, which specifically classifies the function as a

23:16 SUBCLASS r

PCI-to-PCI bridge.

15:8 PGMIF r Programming Interface. This field returns 00h when read.

7:0 CHIPREV r Silicon Revision. This field returns the silicon revision.

4.2.7 Cache Line Size Register

The Cache Line Size Register is implemented by PCI Express devices as a read-write field for legacy

compatibility purposes but has no impact on any PCI Express device functionality.

PCI register offset: 0Ch

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.2.8 Primary Latency Timer Register

This read-only register has no meaningful context for a PCI Express device and returns zeros when read.

PCI register offset: 0Dh

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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Product Folder Link(s): XIO3130