Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 4-4. Bit Descriptions – Status Register
BIT FIELD NAME ACCESS DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP on the
upstream port. This bit is set regardless of the state of the Parity Error Response bit in the Command
Register.
15 PAR_ERR rcu
0 – No parity error detected.
1 – Parity Error detected.
Signaled system error. This bit is set when the XIO3130 sends an ERR_FATAL or ERR_NONFATAL
message upstream, and the SERR Enable bit in the Command Register is set.
14 SYS_ERR rcu
0 – No error signaled.
1 – ERR_FATAL or ERR_NONFATAL signaled.
Received master abort. This bit is set when the upstream PCI Express interface of the XIO3130
receives a Completion with Unsupported Request Status
13 MABORT rcu
0 – Unsupported Request not received.
1 – Unsupported Request received on.
Received target abort. This bit is set when the upstream PCI Express interface of the XIO3130
receives a Completion with Completer Abort Status
12 TABORT_REC rcu
0 – Completer Abort not received.
1 – Completer Abort received.
Signaled target abort. This bit is set when the upstream PCI Express interface completes a Request
with Completer Abort Status.
11 TABORT_SIG rcu
0 – Completer Abort not signaled.
1 – Completer Abort signaled.
10:9 PCI_SPEED r DEVSEL timing. These bits are read only zero because they do not apply to PCI Express.
Master data parity error. This bit is set when the XIO3130 receives a poisoned completion or poisons
8 DATAPAR rcu a write request on the upstream PCI Express interface. This bit is never set if the parity error
response enable bit in the Command register is clear.
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express device and
7 FBB_CAP r
is hardwired to 0.
6 RSVD r Reserved. When read, this bit returns zero.
66 MHz capable. This bit does not have a meaningful context for a PCI Express device and is
5 66MHZ r
hardwired to 0.
Capabilities list. This bit returns 1 when read, indicating that the XIO3130 supports additional PCI
4 CAPLIST r
capabilities.
Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only zero since the
3 INT_STATUS r XIO3130 upstream port does not generate any interrupts internally. The XIO3130 does forward INTx
messages from downstream ports to the upstream port (see INTx Support section).
2:0 RSVD r Reserved. When read, these bits return zeros.
38 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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