Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-3. Bit Descriptions – Command Register
BIT FIELD NAME ACCESS DESCRIPTION
15:11 RSVD r Reserved. When read, these bits return zeros.
INTx disable. This bit is used to enable device-specific interrupts. The XIO3130 upstream port does
10 INT_DISABLE rw not generate any interrupts internally, so this bit is ignored. The XIO3130 does forward INTx
messages from downstream ports to the upstream port.
9 FBB_ENB r Fast back-to-back enable. This bit does not apply to PCI-Express, and returns zero when read.
SERR enable. When set, the XIO3130 can signal fatal and nonfatal errors on the upstream PCI
Express interface.
8 SERR_ENB rw
0 – Disable the reporting of nonfatal errors and fatal errors.
1 – Enable the reporting of nonfatal errors and fatal errors.
7 STEP_ENB r Address/data stepping control. This bit does not apply to PCI-Express and is hardwired to 0.
Parity error response enable. Mask bit for the DATAPAR bit in the Status Register.
0 – The upstream bridge must ignore any address or data parity errors that it detects and
6 PERR_ENB rw continue normal operation.
1 – The upstream bridge must detect address or data parity errors and report them by setting
the DATAPAR bit in the Status Register.
VGA palette snoop enable. The XIO3130 does not support VGA palette snooping, thus this bit
5 VGA_ENB r
returns zero when read.
Memory write and invalidate enable. This bit does not apply to PCI-Express, and is hardwired to
4 MWI_ENB r
zero.
3 SPECIAL r Special cycle enable. This bit does not apply to PCI-Express and is hardwired to zero.
Bus master enable. When set, the XIO3130 is enabled to initiate cycles on the upstream PCI
Express interface.
0 – Upstream PCI Express interface cannot initiate transactions. The bridge must disable
2 MASTER_ENB rw
response to memory and I/O transactions on the PCI interface.
1 – Upstream PCI Express interface can initiate transactions. The bridge can forward memory
and I/O transactions from the secondary interface.
Memory response enable. Setting this bit enables the XIO3130 to respond to memory transactions
1 MEMORY_ENB rw
on the upstream PCI Express interface.
I/O space enable. Setting this bit enables the XIO3130 to respond to I/O transactions on the
0 IO_ENB rw
upstream PCI Express interface.
4.2.5 Status Register
The Status register provides information about the primary interface to the system.
PCI register offset: 06h
Register type: Read Only; Cleared by a Write of One; Hardware Update
Default value: 0010h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
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