Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
4.2.1 PCI Configuration Space (Upstream Port) Register Map
Table 4-1. PCI Express Upstream Port Configuration Register Map (Type 1)
Register Name Offset
Device ID Vendor ID 000h
Status Command 004h
Class Code Revision ID 008h
BIST Header Type Latency Timer Cache Line Size 00Ch
Reserved 010h-014h
Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number 018h
Secondary Status I/O Limit I/O Base 01Ch
Memory Limit Memory Base 020h
Pre-fetchable Memory Limit Pre-fetchable Memory Base 024h
Pre-fetchable Base Upper 32 Bits 028h
Pre-fetchable Limit Upper 32 Bits 02Ch
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits 030h
Reserved Capabilities Pointer 034h
Reserved 038h
Bridge Control Interrupt Pin Interrupt Line 03Ch
Reserved 040h-04Ch
Power Management Capabilities Next-item Pointer PM CAP ID 050h
PM Data (RSVD) PMCSR_BSE Power Management CSR 054h
Reserved 058h-06Ch
MSI Message Control Next-item Pointer MSI CAP ID 070h
MSI Message Address 074h
MSI Upper Message Address 078h
Reserved MSI Message Data 07Ch
Reserved Next-item Pointer SSID/SSVID CAP ID 080h
Subsystem ID Subsystem Vendor ID 084h
Reserved 088h-08Ch
PCI Express Capabilities Register Next-item Pointer PCI Express Capability ID 090h
Device Capabilities 094h
Device Status Device Control 098h
Link Capabilities 09Ch
Link Status Link Control 0A0h
Reserved 0A4h-0ACh
SB Control and Status Serial Bus Slave Address Serial Bus Index Serial Bus Data 0B0h
Upstream Port L1 Idle Upstream Port Link PM Latency 0B4h
Global Chip Control 0B8h
GPIO B Control GPIO A Control 0BCh
GPIO D Control GPIO C Control 0C0h
GPIO Data 0C4h
TI Proprietary 0C8h-0DCh
Subsystem Access 0E0h
General Control 0E4h
Global Switch Control Downstream Ports Link PM Latency 0E8h
Reserved 0ECh-0FCh
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 35
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