Specifications
**Examplevalues.Actualbusnumbers may change based on system hierarchy.
Virtual Internal PCI Bus
Downstream Port
Header Type 01h
PCI Capability
Structures /
Proprietary
Register Space
Extended
Configuration
Space / PCI Express
Capability Structures
000h
03Fh
040h
0FFh
100h
FFFh
Port# 1
Bus# N+2**
Downstream Port
Header Type 01h
PCI Capability
Structures /
Proprietary
Register Space
Extended
Configuration
Space / PCI Express
Capability Structures
000h
03Fh
040h
0FFh
100h
FFFh
Port# 2
Bus# N+3**
Downstream Port
Header Type 01h
PCI Capability
Structures /
Proprietary
Register Space
Extended
Configuration
Space / PCI Express
Capability Structures
000h
03Fh
040h
0FFh
100h
FFFh
Port# 3
Bus# N+4**
Upstream Port
Header Type 01h
PCI Capability
Structures /
Proprietary
Register Space
Extended
Configuration
Space / PCI Express
Capability Structures
000h
03Fh
040h
0FFh
100h
FFFh
Device# 0
Bus# N**
Device# 0 Device# 1 Device# 2
(Bus# N+1**)
Port# 0
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
www.ti.com
Figure 4-1. XIO3130 Enumerations Topology
4.2 PCI Express Upstream Port Registers
The default reset domain for all upstream port registers is IPRST. The internal IPRST reset signal is
asserted when the internally-generated power-on reset is asserted, when GRST is asserted, when PERST
is asserted, or when PCI Express training control hot reset is asserted. Some register fields are placed in
a reset domain different from the default reset domain; all bit or field descriptions identify any unique reset
domains. Generally, all sticky bits are placed in the GRST domain and all (non-sticky) EEPROM loadable
bits are placed in the PERST domain.
34 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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