Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
4 XIO3130 Configuration Register Space
This chapter specifies the configuration registers that are used to enumerate the XIO3130 device within a
PC system.
An overview of the configuration register space is provided along with a detailed description of the register
bits associated with the upstream and downstream ports of the XIO3130.
4.1 PCI Configuration Register Space Overview
Each PCI Express port contains a set of PCI configuration registers. One of the upstream port registers,
the Global Chip Control register, is used to control functions across the entire XIO3130.
For downstream ports, only one register set is specified, but this register set is duplicated for each
downstream port. Figure 4-1 illustrates the enumeration topology.
The XIO3130 must appear as a hierarchy of PCI-to-PCI bridges in the manner outlined by the PCI
Express base specification.
NOTE
This numbering scheme is typical but not ensured. Bus numbers are assigned within the
Type 01h configuration header during the initial enumeration of the PCI bus by the system
at power-up.
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