Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 3-5. Switch Reset Options
Reset Option XIO3130 Feature Reset Response
Internally-generated power-on During a power-on cycle, the XIO3130 asserts an When the internal power-on reset is asserted, all
reset internal reset and monitors the VDDCOMB15 (C01) control registers, state machines, sticky register bits,
terminal. When this terminal reaches 90% of the and power management state machines are
nominal input voltage specification, power is initialized to their default state.
considered stable. After stable power, the XIO3130
monitors the PCI Express reference clock
(REFCLKI) and waits 10 ms after active clocks are
detected. Then, internal power-on reset is
de-asserted.
Global reset input GRST (C02) When GRST is asserted low, an internal power-on When GRST is asserted low, all control registers,
reset occurs. This reset is asynchronous and state machines, sticky register bits, and power
functions during both normal power states and V
AUX
management state machines are initialized to their
power states. default state. When the rising edge of GRST occurs,
the switch samples the state of all static control
inputs and latches the information internally. If an
external serial EEPROM is detected, then a
download cycle is initiated. Also, the process to
configure and initialize the PCI Express link is
started. The switch starts link training within 80 ms
after PERST or GRST is de-asserted.
PCI Express reset input When PERST is asserted low, all control register
This XIO3130 input terminal is used by an upstream
PERST (B01) bits that are not sticky are reset. Also, all state
PCI Express device to generate a PCI Express reset
machines that are not associated with sticky
and to signal a system power good condition.
functionality or V
AUX
power management are reset.
When the rising edge of PERST occurs, the switch
When PERST is asserted low, all control register
samples the state of all static control inputs and
bits that are not sticky are reset. Also, all state
latches the information internally. If an external
machines that are not associated with sticky
serial EEPROM is detected, then a download cycle
functionality or VAUX power management are reset.
is initiated. Also, the process to configure and
When the rising edge of PERST occurs, the switch
initialize the PCI Express link is started. The switch
samples the state of all static control inputs and
starts link training within 80 ms after PERST or
latches the information internally. If an external
GRST is de-asserted.
serial EEPROM is detected, then a download cycle
is initiated. Also, the process to configure and
initialize the PCI Express link is started. The switch
starts link training within 80 ms after PERST or
GRST is de-asserted.
Note: The system must assert PERST before power
is removed, before REFCLKI is removed, or before
REFCLKI becomes unstable.
PCI Express training control The XIO3130 responds to a training control hot In the DL_DOWN state, all remaining configuration
hot reset reset received on the PCI Express interface. After a register bits and state machines are reset. All
training control hot reset, the PCI Express interface remaining bits exclude sticky bits and EEPROM
enters the DL_DOWN state. loadable bits. All remaining state machines exclude
sticky functionality, EEPROM functionality, and V
AUX
power management.
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