Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
This download table must be explicitly followed for the XIO3130 to correctly load initialization values from
a serial EEPROM. All byte locations must be considered when programming the EEPROM.
The XIO3130 addresses the serial EEPROM using a default slave address of 1010_000X binary. For an
EEPROM download operation that occurs immediately after PERST, this address is fixed. The serial
EEPROM in the sample application circuit (Figure 3-4) assumes the 1010b high-address nibble. The lower
three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs
tied to VSS to match the least-significant three address bits.
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is
asserted. After the download is finished, bit 4 is negated. At that time, bit 0 (ROM_ERR) in the serial-bus
control and status register may be monitored to verify a successful download.
3.4.4 Accessing Serial Bus Devices Through Software
The XIO3130 provides a programming mechanism to control serial bus devices through system software.
The programming is accomplished through a doubleword of PCI configuration space at offset B0h.
Table 3-4 lists the registers used to program a serial-bus device through software.
Table 3-4. Register for Programming Serial-Bus Devices
PCI Offset Register Name Description
This register contains the data byte to send on write commands or
B0h Serial-bus data
the received data byte on read commands.
The content of this register is sent as the word address on byte
B1h Serial-bus word address writes or reads. This register is not used in the quick command
protocol.
Write transactions to this register initiate a serial-bus transaction.
B2h Serial-bus slave address The slave device address and the R/W command selector are
programmed through this register.
Serial interface enable, busy, and error status are communicated
B3h Control and Status through this register. In addition, the protocol-select bit and serial
bus test bit are programmed through this register.
To access the serial EEPROM through the software interface, the software performs five steps:
1. Reads the Control and Status Byte to verify that the EEPROM interface is enabled (SBDETECT
asserted) and not busy (REQBUSY and ROMBUSY negated).
2. Loads the Serial Bus word address. If the access is a write, the data byte is also loaded.
3. Writes the Serial Bus slave address and read/write command selector byte.
4. Monitors REQBUSY until this bit is negated.
5. Checks SB_ERR to verify that the serial bus operation completed without error. If the operation is a
read, after REQBUSY is negated, the serial bus data byte is valid.
3.5 Switch Reset Features
Four XIO3130 reset options are available:
• Internally-generated power-on reset
• A global reset generated by asserting GRST input terminal
• A PCI Express reset generated by asserting PERST input terminal
• Software-initiated resets that are controlled by sending a PCI Express training control hot reset
Table 3-5 identifies these reset sources and describes how the XIO3130 responds to each reset.
Copyright © 2007–2010, Texas Instruments Incorporated Description 31
Submit Documentation Feedback
Product Folder Link(s): XIO3130