Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 3-3. EEPROM Register Loading Map (continued)
EEPROM Byte Address Suggested Programmed CONFIG Register Address
Register Description
(hex) Value (hex) (hex)
26 3F 0E9 Downstream Port Link PM Latency register
27 4 0EA Global Switch Control register
28 1 NA Downstream Port 1 Function Indicator
29 0 NA Not used
2A 01 0C8 TI Proprietary register
(1)
2B 0 0CC TI Proprietary register
(1)
2C 0 0CD TI Proprietary register
(1)
2D 0 0D0 TI Proprietary register
(1)
2E 0 0D1 TI Proprietary register
(1)
2F 14 0D2 TI Proprietary register
(1)
30 32 0D3 TI Proprietary register
(1)
31 10 0D4 General Control register
32 60 0D5 General Control register
33 1A 0EC L0s Timeout register
34 0 0EE General Slot Info register
35 0 0EF General Slot Info register
36 2 NA Downstream Port 2 Function Indicator
37 0 NA Not used
38 01 0C8 TI Proprietary register
(1)
39 0 0CC TI Proprietary register
(1)
3A 0 0CD TI Proprietary register
(1)
3B 0 0D0 TI Proprietary register
(1)
3C 0 0D1 TI Proprietary register
(1)
3D 14 0D2 TI Proprietary register
(1)
3E 32 0D3 TI Proprietary register
(1)
3F 10 0D4 General Control register
40 60 0D5 General Control register
41 1A 0EC L0s Timeout register
42 0 0EE General Slot Info register
43 0 0EF General Slot Info register
44 2 NA Downstream Port 3 Function Indicator
45 0 NA Not used
46 01 0C8 TI Proprietary register
(1)
47 0 0CC TI Proprietary register
(1)
48 0 0CD TI Proprietary register
(1)
49 0 0D0 TI Proprietary register
(1)
4A 0 0D1 TI Proprietary register
(1)
4B 14 0D2 TI Proprietary register
(1)
4C 32 0D3 TI Proprietary register
(1)
4D 10 0D4 General Control register
4E 60 0D5 General Control register
4F 1A 0EC L0s Timeout register
50 0 0EE General Slot Info register
51 0 0EF General Slot Info register
30 Description Copyright © 2007–2010, Texas Instruments Incorporated
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