Specifications

S
b6 b1b2b3b4b5 b0 1 A
b7 b6 b1b2b3b4b5 b0 A
Slave Address
Word Address
Start
R/W
S
Restart
b6 b1b2b3b4b5 b0 0 A
Slave Address
R/W
b7 b6 b1b2b3b4b5 b0 M
DataByte
P
A =Slave AcknowledgementM=Master AcknowledgementS/P =Start/StopCondition
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
recognizes the slave address. Next, the XIO3130 sends the EEPROM word address, and another slave
acknowledgment is expected. Then, the XIO3130 issues a restart condition followed by the 7-bit slave
address and the R/W command bit equal to one (read). Once again, the slave device responds with
acknowledge. Next, the slave device sends the 8-bit data byte, MS bit first. Since this is a one-byte read,
the XIO3130 responds with no acknowledge (logic high), indicating the last data byte. Finally, the XIO3130
issues a stop condition.
Figure 3-8. Serial-Bus Protocol – Byte Read
Figure 3-9 illustrates the serial interface protocol during a multiple-byte serial EEPROM download. The
serial bus protocol starts exactly the same way as a one-byte read. The only difference is that multiple
data bytes are transferred. The number of transferred data bytes is controlled by the XIO3130 master.
After each data byte, if more data bytes are requested, the XIO3130 master issues acknowledge (logic
low). The transfer ends after an XIO3130 master no acknowledge (logic high), followed by a stop
condition.
Figure 3-9. Serial-Bus Protocol – Multiple-Byte Read
The PROT_SEL bit (bit 7) in the Serial Bus Control and Status register changes the serial bus protocol.
Each of the three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low).
When this control bit is asserted, the word address and corresponding acknowledge are removed from the
serial bus protocol. This feature allows the system designer a second serial bus protocol option when
selecting external EEPROM devices.
3.4.3 Serial Bus EEPROM Application
The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3-3.
Note the following:
• EEPROM bytes 00h through 1Dh affect the general control options for the XIO3130.
• EEPROM bytes 1Eh through 27h affect the operation of the upstream port (port 0).
• Bytes 00h through 27h are loaded into the configuration registers for the upstream virtual bridge or port
0 (see Figure 4-1).
28 Description Copyright © 2007–2010, Texas Instruments Incorporated
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