Specifications

XIO3130
SCL
SDA
SERIAL
EEPROM
SCL A2
A1
SDA A0
VDD3 3
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
edge of PERST or GRST, whichever occurs last, the SCL terminal is checked for a pullup resistor. If one
is detected, bit 3 (SBDETECT) in the serial bus control and status register (see Table 4-32) is set.
Software may disable the serial bus interface at any time by writing a zero to the SBDETECT bit. If no
external EEPROM is required, the serial bus interface is permanently disabled by attaching a pulldown
resistor to the SCL signal.
The XIO3130 implements a two-terminal serial interface with one clock signal (SCL) and one data signal
(SDA). The SCL signal is a unidirectional output from the XIO3130 and the SDA signal is bidirectional.
Both are open-drain signals and require pullup resistors. The XIO3130 is a bus master device and drives
SCL at approximately 60 kHz during data transfers and places SCL in a high-impedance state during bus
idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address equal to
1010_000X binary. Figure 3-4 illustrates a sample application implementing the two-wire serial bus.
Figure 3-4. Serial EEPROM Applications
3.4.2 Serial Bus Interface Protocol
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a
start condition, which is signaled when the SDA line transitions to a low state while SCL is in the high
state, as illustrated in Figure 3-5. The end of a requested data transfer is indicated by a stop condition,
which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-5.
Data on SDA must remain stable during the high state of the SCL signal because changes on the SDA
signal during the high state of SCL are interpreted as control signals (i.e., a start or a stop condition).
26 Description Copyright © 2007–2010, Texas Instruments Incorporated
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