Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 3-2. Messages Supported by the XIO3130
Message Supported XIO3130 Action
Assert_INTx Yes Passed through upstream
Deassert_INTx Yes Passed through upstream
PM_Active_State_Nak Yes Received and processed
Passed through upstream
PM_PME Yes
Downstream PCI Hot Plug Event: Initiated upstream
Received and processed
PME_Turn_Off Yes
Passed through downstream
Downstream port: Received and processed
PME_TO_Ack Yes
Downstream ports: Initiated upstream
Passed through upstream
ERR_COR Yes
Initiated upstream
Passed through upstream
ERR_NONFATAL Yes
Initiated upstream
Passed through upstream
ERR_FATAL Yes
Initiated upstream
Received and processed
Unlock Yes
Passed through downstream
Upstream port: Received and processed
Set_Slot_Power_Limit Yes
Downstream port: Initiated downstream
Advanced Switching Messages No Discarded
Upstream port: Unsupported request
Vendor Defined Type 0 Yes
Passed through downstream
Upstream port: Discarded
Vendor Defined Type 1 Yes
Passed through downstream
All supported message transactions are processed according to the PCI Express Base Specification.
3.3 GPIO Terminals
Up to 19 general-purpose input/output (GPIO) terminals are provided for system customization. These
GPIO terminals are 3.3-V tolerant.
The exact number of GPIO terminals available varies based on the implementation of various supported
functions that share GPIO terminals. When any of the shared functions are enabled, the associated GPIO
terminal is disabled. When pulled high, the DPSTRP terminals cause some GPIO terminals to be mapped
to PCI Hot Plug functions for specific ports. Additional information can be found in the DPSTRP pin
descriptions and in Chapter 4.
All GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding
bits in the GPIOA, GPIOB, GPIOC, or GPIOD Control Registers. The GPIO data register is used to
monitor GPIO terminals defined as inputs or to set the state of GPIO terminals defined as outputs. For
more information on GPIO terminals, see sections Section 4.2.61 through Section 4.2.65.
3.4 Serial EEPROM
The XIO3130 provides a two-wire serial-bus interface to load subsystem identification information and
specific register defaults from an external EEPROM. This interface supports slow, fast, and high-speed
EEPROM speed options.
3.4.1 Serial Bus Interface Implementation
To enable the serial bus interface, a pullup resistor must be implemented on the SCL signal. At the rising
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