Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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3.2.3 Beacon

The XIO3130 supports the PCI Express in-band beacon feature. Beacon is driven on the PCI Express link

by the XIO3130 to request the re-application of main power when in the L2 link state. Once beacon is

activated, the XIO3130 continues to send the beacon signal until main power is restored as indicated by

PERST going inactive. At this time, the beacon signal is deactivated.

3.2.4 WAKE

The XIO3130 supports the PCI Express sideband WAKE feature. WAKE is an active-low signal driven by

the XIO3130 to request the re-application of main power when in the L2 link state. Since WAKE is an

open-collector output, a system-side pullup resistor is required to prevent the signal from floating. If WAKE

to Beacon translation is enabled (see section 3.2.60), the XIO3130 detects when WAKE is asserted and

transmits beacon to alert the system. This enables support for devices that use the WAKE protocol in a

system that does not support it.

3.2.5 Initial Flow Control Credits

The XIO3130 flow control credits are initialized using the rules defined in the PCI Express Base

Specification. Table 3-1 identifies the initial flow control credit advertisement for the XIO3130. The initial

advertisement is exactly the same for both upstream and downstream ports.

Table 3-1. Initial Flow Control Credit Advertisements

Initial Advertisement

Credit Type

Hex Decimal

Posted Request Headers (PH) 10 16

Posted Request Data (PD) 80 128

Non-Posted Header (NPH) 10 16

Non-Posted Data (NPD) 10 16

Completion Header (CPLH) 10 16

Completion Data (CPLD) 80 128

3.2.6 PCI Express Message Transactions

PCI Express messages are initiated by, received by and passed through the XIO3130. Table 3-2 outlines

message support within the switch.

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Product Folder Link(s): XIO3130