Specifications

PCI
Express
X1 Phy
Port0
(Up)
Logic
Virtual
PCIto
PCI
Bridge
Port1
(Down)
Logic
Port2
(Down)
Logic
Port3
(down)
logic
GPIO
PCI Hot
Plug
EEPROM
Clock
Distribution/
ResetLogic
Virtual
PCIto
PCIBridge
Bridge
Virtual
PCIto
PCIBridge
Bridge
Virtual
PCIto
PCIBridge
Bridge
PCI
Expressx1
Phy
PCI
Expressx1
Phy
PCI
Expressx1
Phy
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
3 Description
Figure 3-1 is the block diagram of the XIO3130.
Figure 3-1. Block Diagram
3.1 Power-Up/Power-Down Sequencing
The following sections describe the procedures to power up and power down the XIO3130 switch.
3.1.1 Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages in any order with any time relationship and with any ramp rate.
3. Apply a stable PCI Express reference clock.
To meet PCI Express specification requirements, PERST cannot be de-asserted until the following two
delay requirements are satisfied:
• Wait a minimum of 100 ms after applying a stable PCI Express reference clock. The 100-ms limit
satisfies the requirement for stable device clocks by the de-assertion of PERST.
• Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the de-assertion of PERST.
See Figure 3-2, Power-Up Sequence Diagram.
22 Description Copyright © 2007–2010, Texas Instruments Incorporated
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