Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 2-11. Miscellaneous Terminals
Signal Ball I/O Type External Parts Description
C02 LV CMOS IN Global power-on reset input. Note: a pullup to Vaux (if supported) or
GRST See description VDD3.3 (if not) is required unless this terminal is always driven by
the upstream device.
SDA D13 LV CMOS I/O Serial Data. This pin is the serial data pin for the EEPROM interface.
B14 LV CMOS O Serial Clock. This pin is the serial clock pin for the EEPROM
SCL
interface.
N02 LV CMOS O Upstream Clock Request. When asserted low, requests upstream
CLKREQ_UP device restart clock in cases where upstream clock may be removed
in L1
RSVD A13, B12, Reserved. These terminals must tied to VDD15.
RSVD C04, P01 Reserved. This terminal must be tied to GND.
RSVD D04 See description Reserved. Pullup to Vaux (if supported) or VDD3.3 (if not)
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