Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Contents
1 Features ........................................................................................................................... 11
2 Introduction ...................................................................................................................... 12
2.1 Description ................................................................................................................. 12
2.2 Related Documents ....................................................................................................... 12
2.3 Document Conventions ................................................................................................... 13
2.4 Ordering Information ...................................................................................................... 13
2.5 Terminal Assignments .................................................................................................... 14
2.6 Terminal Descriptions ..................................................................................................... 17
3 Description ....................................................................................................................... 22
3.1 Power-Up/Power-Down Sequencing .................................................................................... 22
3.1.1 Power-Up Sequence ........................................................................................... 22
3.1.2 Power-Down Sequence ........................................................................................ 23
3.2 Express Interface .......................................................................................................... 23
3.2.1 External Reference Clock ..................................................................................... 23
3.2.2 Clock Generator ................................................................................................ 23
3.2.3 Beacon ........................................................................................................... 24
3.2.4 WAKE ............................................................................................................ 24
3.2.5 Initial Flow Control Credits .................................................................................... 24
3.2.6 PCI Express Message Transactions ......................................................................... 24
3.3 GPIO Terminals ............................................................................................................ 25
3.4 Serial EEPROM ............................................................................................................ 25
3.4.1 Serial Bus Interface Implementation ......................................................................... 25
3.4.2 Serial Bus Interface Protocol .................................................................................. 26
3.4.3 Serial Bus EEPROM Application ............................................................................. 28
3.4.4 Accessing Serial Bus Devices Through Software .......................................................... 31
3.5 Switch Reset Features .................................................................................................... 31
4 XIO3130 Configuration Register Space ................................................................................. 33
4.1 PCI Configuration Register Space Overview .......................................................................... 33
4.2 PCI Express Upstream Port Registers ................................................................................. 34
4.2.1 PCI Configuration Space (Upstream Port) Register Map ................................................. 35
4.2.2 Vendor ID Register ............................................................................................. 36
4.2.3 Device ID Register ............................................................................................. 36
4.2.4 Command Registers ........................................................................................... 36
4.2.5 Status Register .................................................................................................. 37
4.2.6 Class Code and Revision ID Register ....................................................................... 39
4.2.7 Cache Line Size Register ..................................................................................... 39
4.2.8 Primary Latency Timer Register .............................................................................. 39
4.2.9 Header Type Register .......................................................................................... 40
4.2.10 BIST Register ................................................................................................... 40
4.2.11 Primary Bus Number ........................................................................................... 40
4.2.12 Secondary Bus Number ....................................................................................... 40
4.2.13 Subordinate Bus Number ...................................................................................... 41
4.2.14 Secondary Latency Timer Register .......................................................................... 41
4.2.15 I/O Base Register ............................................................................................... 41
4.2.16 I/O Limit Register ............................................................................................... 42
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