Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 2-8. PCI Express Terminals
Signal Ball I/O Type External Parts Description
UP_PETp G01 HS DIFF
Series capacitors High-speed differential transmit pair for upstream port 0
UP_PETn G02 OUT
DN1_PETp A08 HS DIFF
Series capacitors High-speed differential transmit pair for downstream port 1
DN1_PETn B08 OUT
DN2_PETp H13 HS DIFF
Series capacitors High-speed differential transmit pair for downstream port 2
DN2_PETn H14 OUT
DN3_PETp N07 HS DIFF
Series capacitors High-speed differential transmit pair for downstream port 3
DN3_PETn P07 OUT
UP_PERp J01
HS DIFF IN High-speed differential receiver pair for upstream port 0
UP_PERn J02
DN1_PERp A06
HS DIFF IN High-speed differential receiver pair for downstream port 1
DN1_PERn B06
DN2_PERp F13
HS DIFF IN High-speed differential receiver pair for downstream port 2
DN2_PERn F14
DN3_PERp N09
HS DIFF IN High-speed differential receiver pair for downstream port 3
DN3_PERn P09
REFR0 D02 External bias External reference resistor terminals for setting TX driver current. An
Passive
REFR1 E03 resistor external resistor is connected between these terminals.
PCI-Express reset input. When logic high, the PERST signal
System-side identifies that the system power is stable. When logic low, the
UP_PERST B01 LV CMOS IN
pullup resistor PERST signal generates an internal power-on reset.
Note: The UP_PERST input buffer has hysteresis.
DN1_PERST B05 LV CMOS O Pulldown resistor PCI-Express reset output for downstream port 1.
DN2_PERST A02 LV CMOS O Pulldown resistor PCI-Express reset output for downstream port 2.
DN3_PERST A01 LV CMOS O Pulldown resistor PCI-Express reset output for downstream port 3.
WAKE is an active low signal that is driven low to reactivate the
System-side PCI-Express link hierarchy’s main power rails and reference clocks.
WAKE C03 LV CMOS I/O
pullup resistor
Note: Since WAKE is an open-drain output buffer, a system-side
pullup resistor is required.
Table 2-9. PCI Hot Plug Strapping Terminals
Signal Ball I/O Type External Parts Description
Downstream Port 1 Strap. This pin is pulled high at the de-assertion of
reset. GPIO0, GPIO1, and GPIO2 are used as PCI Hot Plug terminals
DN1_DPSTR Pullup or pulldown for downstream port 1 and are no longer available for use as GPIOs.
C10 LV CMOS IN
P resistor The three terminals become PRESENT, PWR_ON, and PWR_GOOD
respectively. These GPIOs are available for normal use if this terminal
is pulled low at the de-assertion of reset.
Downstream Port 2 Strap. This pin is pulled high at the de-assertion of
reset. GPIO4, GPIO5, and GPIO6 are used as PCI Hot Plug terminals
DN2_DPSTR Pullup or pulldown for downstream port 2 and are no longer available for use as GPIOs.
L13 LV CMOS IN
P resistor The three terminals become PRESENT, PWR_ON, and PWR_GOOD
respectively. These GPIOs are available for normal use if this terminal
is pulled low at the de-assertion of reset.
Downstream Port 3 Strap. This pin is pulled high at the de-assertion of
reset. GPIO8, GPIO9, and GPIO10 are used as PCI Hot Plug terminals
DN3_DPSTR Pullup or pulldown for downstream port 3 and are no longer available for use as GPIOs.
N04 LV CMOS IN
P resistor The three terminals become PRESENT, PWR_ON, and PWR_GOOD
respectively. These GPIOs are available for normal use if this terminal
is pulled low at the de-assertion of reset.
Copyright © 2007–2010, Texas Instruments Incorporated Introduction 19
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