Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

www.ti.com

Table 2-6. Ground Terminals

Signal Ball I/O Type Description

D05, D06, D10, D11, E05,

E06, E07, E08, E09, E10,

E11, E12, F05, F06, F07,

F08, F09, F10, G05, G06,

G07, G08, G09, G10,

VSS GND Digital ground terminals

H05, H06, H07, H08, H09,

H10, J05, J06, J07, J08,

J09, J10, K02, K05, K06,

K07, K08, K09, K10, K11,

L04, L05, L10, L11, M05

VSSA(0) G03, H01, K01 GND Analog ground terminals for upstream Port 0

VSSA(1) A05, A10, C07, C08, C09 GND Analog ground terminals for downstream Port 1

E14, F11, F12, G14, H12,

VSSA(2) GND Analog ground terminals for downstream Port 2

J13, K13

L09, M07, M09, N05, N06,

VSSA(3) GND Analog ground terminals for downstream Port 3

P08, P10

VSSAREF E04 GND 1.5-V PCI-Express analog reference ground terminal

VSSDREF D01 GND 1.5-V PCI-Express digital reference ground terminal

Table 2-7. PCI Express Reference Clock Terminals

Signal Ball I/O Type External Parts Description

UP_REFCKIp L01 Reference clock inputs. REFCKIp and REFCKIn comprise the

HS DIFF IN

UP_REFCKIn L02 differential input pair for the 100-MHz system reference clock.

DN1_REFCKOp A09

HS DIFF OUT 100 MHz differential reference clock outputs for downstream port 1

DN1_REFCKOn B09

DN2_REFCKOp K14

HS DIFF OUT 100 MHz differential reference clock outputs for downstream port 2

DN2_REFCKOn J14

DN3_REFCKOp P05

HS DIFF OUT 100 MHz differential reference clock outputs for downstream port 3

DN3_REFCKOn P06

Submit Documentation Feedback

Product Folder Link(s): XIO3130