Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
6.6 PCI Express Reference Clock Output Requirements
100-MHz INPUT
SYMBOL PARAMETER UNIT NOTES
MIN MAX
Rise Edge Rate Rising edge rate 0.6 4 V/ns See
(1)
and
(2)
.
Fall Edge Rate Falling edge rate 0.6 4 V/ns See
(1)
and
(2)
.
V
IH
Differential input high voltage 150 mV See
(1)
.
V
IL
Differential input low voltage –150 mV See
(1)
.
V
CROSS
Absolute crossing point voltage 250 550 mV See Notes
(3)
,
(4)
, and
(5)
.
R
CROSS DELTA
Variation of V
CROSS
over all rising
140 mV See Notes
(3)
,
(4)
, and
(6)
.
clock edges
V
RB
Ring-back voltage margin –100 100 mV See
(1)
and
(7)
.
T
STABLE
Time before V
RB
is allowed 500 ps See
(1)
and
(7)
.
T
PERIOD AVG
Average clock period accuracy –300 2800 ppm See Notes
(1)
,
(8)
, and
(9)
.
T
PERIOD ABS
Absolute period (including jitter and
9.847 10.203 ns See
(1)
and
(10)
.
spread spectrum)
T
CCJITTER
Cycle-to-cycle jitter 150 ps See
(1)
.
V
MAX
Absolute maximum input voltage 1.15 V See
(3)
and
(11)
.
V
MIN
Absolute minimum input voltage –0.3 V See
(3)
and
(12)
.
Duty Cycle Duty cycle 40 60 % See
(1)
.
Rise-Fall Rising edge rate (REFCKOp) to
Matching falling edge rate (REFCKOn) 20 % See
(3)
and
(13)
.
matching
Z
C-DC
Clock source DC impedance 40 60 Ω See
(3)
and
(14)
.
(1) Measurement taken from differential waveform.
(2) Measured from –150 mV to +150 mV on the differential waveform (derived from REFCKOp minus REFCKOn). The signal must be
monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero
crossing.
(3) Measurement taken from single-ended waveform.
(4) Measured at crossing point where the instantaneous voltage value of the rising edge of REFCKOp equals the falling edge of REFCKOn.
(5) Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
(6) Defined as the total variation of all crossing voltages of rising REFCKOp and falling REFCKOn. This is the maximum allowed variance in
VCROSS for any particular system.
(7) TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is
allowed to droop back into the VRB ±100 mV differential range.
(8) Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations.
(9) PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly
or 100 Hz. For 300 PPM then we have a error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a
frequency counter with measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread
Spectrum or that use common clock source. For systems employing Spread Spectrum there is an additional 2500 PPM nominal shift in
maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800 PPM.
(10) Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and
spread spectrum modulation.
(11) Defined as the maximum instantaneous voltage including overshoot.
(12) Defined as the minimum instantaneous voltage including undershoot.
(13) Matching applies to rising edge rate for REFCKOp and falling edge rate for REFCKOn. It is measured using a ±75 mV window centered
on the median cross point where REFCKOp rising meets REFCKOn falling. The median cross point is used to calculate the voltage
thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCKOp should be compared to the Fall
Edge Rate of REFCKOn, the maximum allowed difference should not exceed 20% of the slowest edge rate.
(14) System board compliance measurements must use the recommended test load card. REFCKOp and REFCKOn are to be measured at
the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single
ended probes with math or differential probe can be used for differential measurements. Test load CL = 2 pF.
138 Electrical Characteristics Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): XIO3130