Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
PCI Express Differential Receiver Input Ranges (continued)
PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS
Measured over 50 MHz to 1.25 GHz with the P
RL
RX-DIFF
PERP, and N lines biased at +300 mV and –300 mV,
10 dB
Differential return loss PERN respectively.
See
(4)
Measured over 50 MHz to 1.25 GHz with the P
RL
RX-CM
PERP, and N lines biased at +300 mV and –300 mV,
6 dB
Common mode return loss PERN respectively.
See
(4)
.
Z
RX-DIFF-DC
PERP, RX DC differential mode impedance.
80 100 120 Ω
DC differential input impedance PERN See
(5)
.
Required RX-D+ as well as RX-D– DC impedance
Z
RX-DC
PERP,
40 50 60 Ω (50 Ω ±20% tolerance).
DC input impedance PERN
See
(1)
and
(5)
.
Required RX-D+ as well as RX-D– DC impedance
Z
RX-HIGH-IMP-DC
PERP,
200K Ω when the receiver terminations do not have power.
Powered-down DC input impedance PERN
See
(6)
.
V
RX-IDLE-DET-DIFFp-p
PERP, V
RX-IDLE-DET-DIFFp-p
= 2 * |V
RX-D+
– V
RX-D–
|
65 175 mV
Electrical idle detect threshold PERN measured at the receiver package pins
An unexpected electrical idle (V
RX-DIFFp-p
<
T
RX-IDLE-DET-DIFF-ENTER-TIME
V
RX-IDLE-DET-DIFFp-p
) must be recognized no longer
PERP,
Unexpected electrical idle enter 10 ms than
PERN
detect threshold integration time T
RX-IDLE-DET-DIFF-ENTER-TIME
to signal an
unexpected idle condition.
(4) The Receiver input impedance shall result in a differential return loss greater than or equal to 10 dB with a differential test input signal of
no less than 200 mV (peak value, 400 mV differential peak to peak) swing around ground applied to D+ and D– lines and a common
mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance
requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 Ω to ground for both the
D+ and D– line (i.e., as measured by a Vector Network Analyzer with 50 Ω probes; see Figure 4-25 in the specification). Note that the
series capacitors CTX is optional for the return loss measurement.
(5) Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM) there is a 5
ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
(6) The RX DC common mode impedance that exists when no power is present or Fundamental Reset is asserted. This helps ensure that
the Receiver Detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 200 mV
above the RX ground.
6.5 PCI Express Differential Reference Clock Input Ranges
(1)
PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS
f
IN-DIFF
REFCKIp The input frequency is 100 MHz +300 ppm and
100 MHz
Differential input frequency REFCKIn –2800＝ppm including SSC-dictated variations.
V
RX-DIFFp-p
REFCKIp
Differential input peak-to-peak 0.175 1.2 V V
RX-DIFFp-p
= 2*|V
REFCKp
– V
REFCKn|
REFCKIn
voltage
V
RX-CM-ACp
V
RX-CM-ACp
= RMS(|V
REFCKp
+ V
REFCKn
|/2 –
REFCKIp
AC peak common mode input 140 mV V
RX-CM-DC
)
REFCKIn
voltage V
RX-CM-DC
= DC
(avg)
of |V
REFCKp
+ V
REFCKn
|/2
REFCKIp
Duty cycle 40% 60% Differential waveform input duty cycle
REFCKIn
Z
RX-DIFF-DC
REFCKIp REFCKIp/ REFCKIn DC differential mode
20 kΩ
DC differential input impedance REFCKIn impedance
(1) The XIO3130 is compliant with the defined system jitter models for a PCI Express reference clock and associated TX/RX link. These
system jitter models are described in the PCI Express Jitter Modeling, Revision 1.0RD document. Any usage of the XIO3130 in a
system configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter
budgets.
Copyright © 2007–2010, Texas Instruments Incorporated Electrical Characteristics 137
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