Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
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Table 4-89. Correctable Error Mask Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Bad DLLP error mask.
7 BAD_DLLP_MASK rwh 0 – Error condition is unmasked
1 – Error condition is masked
Bad TLP error mask.
6 BAD_TLP_MASK rwh 0 – Error condition is unmasked
1 – Error condition is masked
5:1 RSVD r Reserved. Return zeros when read.
Receiver error mask.
0 RX_ERROR_MASK rwh 0 – Error condition is unmasked
1 – Error condition is masked
4.3.71 Advanced Error Capabilities and Control Register
The Advanced Error Capabilities and Control register allows the system to monitor and control the
advanced error reporting capabilities.
PCI register offset: 118h
Register type: Read Only, Read/Write
Default value: 0000 00A0h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0
Table 4-90. Advanced Error Capabilities and Control Register
BIT FIELD NAME ACCESS DESCRIPTION
31:9 RSVD r Reserved. Return zeros when read.
Extended CRC check enable.
8 ECRC_CHK_EN rwh 0 – Extended CRC checking is disabled
1 – Extended CRC checking is enabled
Extended CRC check capable. This read-only bit returns a value of ‘1’ indicating
7 ECRC_CHK_CAPABLE r
that the bridge is capable of checking extended CRC information.
Extended CRC generation enable.
6 ECRC_GEN_EN rwh 0 – Extended CRC generation is disabled
1 – Extended CRC generation is enabled
Extended CRC generation capable. This read-only bit returns a value of ‘1’
5 ECRC_GEN_CAPABLE r
indicating that the bridge is capable of generating extended CRC information.
First error pointer. This five-bit value reflects the bit position within the
4:0 FIRST_ERR rh Uncorrectable Error Status register corresponding to the class of the first error
condition that was detected.
4.3.72 Header Log Register
The Header Log register stores the TLP header for the packet that lead to the most recently detected error
condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a
4DW TLP header).
PCI register offset: 11Ch – 128h
126 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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