Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-88. Correctable Error Status Register
BIT FIELD NAME ACCESS DESCRIPTION
31:14 RSVD r Reserved. Return zeroes when read.
13 ANFES rcuh Advisory nonfatal error status.
Replay timer timeout. This bit is asserted when the replay timer expires for a pending request
12 REPLAY_TMOUT rcuh
or completion that has not been acknowledged.
11:9 RSVD r Reserved. Return zeroes when read.
REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over when a
8 REPLAY_ROLL rcuh
pending request of completion has not been acknowledged.
Bad DLLP error. This bit is asserted when an 8b/10n error is detected by the PHY during
7 BAD_DLLP rcuh
reception of a DLLP.
Bad TLP error. This bit is asserted when an 8b/10b error is detected by the PHY during
6 BAD_TLP rcuh
reception of a TLP.
5:1 RSVD r Reserved. Return zeros when read.
0 RX_ERROR rcuh Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any time.
4.3.70 Correctable Error Mask Register
The Correctable Error Mask register controls the reporting of individual errors as they occur. When a bit is
set to one, error status bits are still affected, but the error is not logged and no error reporting message is
sent upstream.
PCI register offset: 114h
Register type: Read Only, Read/Write
Default value: 0000 2000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-89. Correctable Error Mask Register
BIT FIELD NAME ACCESS DESCRIPTION
31:14 RSVD r Reserved. Return zeros when read.
Advisory nonfatal error mask. This bit is set by default to enable compatibility with
13 ANFEM rwh
software that does not comprehend role-based error reporting.
Replay timer timeout mask.
12 REPLAY_TMOUT_MASK rwh 0 – Error condition is unmasked
1 – Error condition is masked
11:9 RSVD r Reserved. Return zeros when read.
REPLAY_NUM rollover mask.
8 REPLAY_ROLL_MASK rwh 0 – Error condition is unmasked
1 – Error condition is masked
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 125
Submit Documentation Feedback
Product Folder Link(s): XIO3130