Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 4-83. Bit Descriptions – General Control Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Electromechanical interlock present. This bit indicates whether an electromechanical interlock is
implemented on the chassis for this slot. This bit is used to control the EMILP field in the Slot
Capabilities register.
5 SLOT_EMILP rw
0 – Electromechanical interlock not implemented
1 – Electromechanical interlock implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Link active reporting capable. This bit indicates whether this slot is capable of reporting whether
the link is active. This bit is used to control the DLL_LARC field in the Link Capabilities register.
This field is used to control the SDERC field in the Link Capabilities register.
LINK_ACT_RPT_CA
4 rw
0 – Slot is not link active reporting capable
P
1 – Slot is link active reporting capable
This field is loaded from EEPROM (if present) and reset with PERST.
This bit is a reserved diagnostic bit that must be set to 0 for proper operation. If an EEPROM is
3 RSVD rw
used, the corresponding bit in the EEPROM must be set to 0.
2 RSVD r Reserved. When read, this bit returns zero.
Reference clock disable. This bit is used to disable the REFCK output.
0 – REFCK enabled
1 REFCK_DIS rw
1 – REFCK disabled
This field is loaded from EEPROM (if present) and reset with PERST.
Receiver presence detect enable. This bit selects whether the PRSNT pin or receiver detect us
used to determine whether the slot is present.
0 – PRSNT pin is used to determine whether slot is present
0 RCVR_PRSNT_EN rw 1 – Receiver detect is used to determine whether slot is present. It is recommended to only use
this option when PRSNT is not available and the card is removable.
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is the inverse of the DNn_DPSTRP pin for the associated port.
4.3.62 L0s Idle Timeout Register
This read/write register controls the idle timeout for initiating L0s entry on the Tx path. The value is in units
of 256 ns. The default value is set for just under 7 ＝s. The minimum timeout is 256 ns. This register is
loaded from serial EEPROM and is reset with PERST.
PCI register offset: ECh
Register type: Read/Write
Default value: 1Ah
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 1 0 1 0
4.3.63 General Slot Info Register
This read/write register contains information that is used in the slot capabilities and control registers for the
downstream port.
PCI register offset: EEh
Register type: Read/Write; Read Only
Default value: 0000h
120 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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