Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

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2 Introduction

The Texas Instruments XIO3130 switch is an integrated PCI Express fanout switch solution with one

upstream x1 port and three downstream x1 ports. This high-performance integrated solution provides the

latest in PCI Express switch technology including cut-through architecture, integrated reference clock

buffers for downstream ports, integrated main power/V

AUX

power switch, and downstream port PCI Hot

Plug® support.

The reader is assumed to have prior knowledge of the PCI Express interface and associated terminology

and of the PCI-SIG specifications.

2.1 Description

The Texas Instruments XIO3130 switch is a PCI Express ×1 3-port fanout switch. The XIO3130 provides a

single x1 upstream port supporting full 250-MB/s packet throughput in each direction simultaneously.

Three independently configurable ×1 downstream ports are provided that also support full 250-MB/s

packet throughput in each direction simultaneously.

A cut-through architecture is implemented to reduce the latency associated with packets moving through

the PCI Express fabric. As soon as the address or routing information is decoded within the header of a

packet entering an ingress port, the packet is directed to the egress port for forwarding. Packet poisoning

using the EDB framing signal is supported in circumstances where packet errors are detected after the

transmission of the egress packet begins.

The downstream ports may be configured to support PCI Hot Plug slot implementations. In this scenario,

the system designer may decide to use the integrated PCI Hot Plug-compliant controller. This feature is

available through the classic PCI configuration space under the PCI Express Capability Structure. When

enabled, the downstream ports provide the PCI Hot Plug standard mechanism to apply and remove power

to the slot or socket.

Power-management features include Active State Power Management, PME mechanisms, the

Beacon/Wake protocol, and all conventional PCI D-states. When ASPM is enabled, each link

automatically saves power when idle using the L0s and L1 states. PME messages are supported along

with the PME_Turn_Off/PME_TO_Ack protocol.

When enabled, the upstream port supports Beacon transmission as well as the WAKE side band signal to

wake the system as the result of a PCI Hot Plug event. Furthermore, the downstream ports may be

configured to detect Beacon from downstream devices and forward this upstream. The switch also

supports the translation and forwarding of WAKE from a downstream device into Beacon on the upstream

port for cabled implementations.

2.2 Related Documents

Trademarks

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Product Folder Link(s): XIO3130