Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
www.ti.com
4.3.60 TI Proprietary Register
This read/write TI proprietary register is located at offset D0h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be 3214
0000h.
PCI register offset: D0h
Register type: Read/Write
Default value: 3214 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.61 General Control Register
This read/write register is used to control various functions of the XIO3130 downstream port.
PCI register offset: D4h
Register type: Read/Write; Read Only
Default value: 0000 x0xx
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 x x 0 0 0 0 0 x 0 0 1 0 0 0 x
Table 4-83. Bit Descriptions – General Control Register
BIT FIELD NAME ACCESS DESCRIPTION
31:17 RSVD r Reserved. When read, these bits return zeros.
16 TI_PROPRIETARY rw TI proprietary. This bit must not be changed from the specified default state.
REFCK power fault control. This bit controls whether REFCK output should be disabled when
PWR_FAULT is asserted.
0 – REFCK output enable is not a function of PWR_FAULT.
15 RC_PF_CTL rw
1 – REFCK output enable is a function of PWR_FAULT.
This field is loaded from EEPROM (if present) and reset with PERST.
PCI Hot Plug capable. This bit indicates whether this slot is capable of PCI Hot Plug operations.
This bit is used to control the PCI Hot Plug capable (HPC) field in the Slot Capabilities register.
0 – Slot is not PCI Hot Plug capable.
14 SLOT_HPC rw
1 – Slot is PCI Hot Plug capable.
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is that of the DNn_DPSTRP pin for the associated port.
118 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): XIO3130