Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-82. Bit Descriptions – Slot Status Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
MRL sensor changed. This bit indicates whether the state of the MRLSS bit has changed.
2 MRLSC ruc 0 – MRLSS bit has not changed.
1 – MRLSS bit has changed.
Power fault detected. This bit indicates the state of the PWRFLT pin.
1 PFD ruc 0 – PWRFLT pin de-asserted (no power fault at slot).
1 – PWRFLT pin asserted (power fault at slot).
Attention button pressed. This bit indicates a de-asserted-to-asserted transition on a
de-bounced derivative of the ATN_BTN pin.
0 ABP ruc
0 – Attention button not pressed
1 – Attention button pressed
4.3.58 TI Proprietary Register
This read/write TI proprietary register is located at offset C8h and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be 0000
0001h.
PCI register offset: C8h
Register type: Read/Write
Default value: xxxx 0001
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
4.3.59 TI Proprietary Register
This read/write TI proprietary register is located at offset CCh and controls TI proprietary functions. This
register must not be changed from the specified default state. If the default value is changed in error, a
PCI Express Reset (PERST) returns this register to a default state.
If an EEPROM is used to load configuration registers, the value loaded for this register must be 0000
0000h.
PCI register offset: CCh
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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