Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 4-81. Bit Descriptions – Slot Control Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Attention button pressed enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the ABP bit in the Slot Status register is asserted.
0 ABP_EN rw
0 – Disabled
1 – Enabled
HPI_EN and MSI_EN (see Table 3ἱ21) must also be enabled for interrupt generation. PME_EN
must also be enabled for PME signaling during D1, D2, or D3hot. For more information, see
section 6.7.7 in PCI Express Base Specification Revision 1.0a.
4.3.57 Slot Status Register
The Slot Status register provides information about slot-specific parameters.
PCI register offset: AAh
Register type: Read Only; Clear by a Write of One; Hardware Update
Default value: 0010h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Table 4-82. Bit Descriptions – Slot Status Register
BIT FIELD NAME ACCESS DESCRIPTION
15:9 RSVD r Reserved. When read, these bits return zeros.
Data link layer state changed. This bit is set when the DLL_ACTV field in the Link Status
8 DLLSC ruc
register changes state. A write of 1’b1 clears this field. A write of 1’b0 has no effect.
Electromechanical interlock status. If an electromechanical interlock is implemented for the
slot, this field indicates the current status of the electromechanical interlock.
7 EMIL_STAT r
0 – Electromechanical interlock disengaged
1 – Electromechanical interlock engaged
Presence detect state. This bit indicates whether a card is present in a slot. If the
SLOT_PRSNT bit in the General Control register is de-asserted, this bit always reads back
asserted. If the SLOT_PRSNT bit is asserted, this bit indicates the state of a de-bounced
6 PDS ru
derivative of the PRSNT input pin.
0 – Card presence detection output de-asserted (i.e., slot empty)
1 – Card presence detection output asserted (i.e., card present in slot)
Manual retention latch sensor state. This bit indicates the state of a de-bounced derivative of
the MRLS_DET input pin.
5 MRLSS ru
0 – MRLS_DET pin asserted (i.e., MRL closed)
1 – MRLS_DET pin de-asserted (i.e., MRL open)
Command completed. This bit is set when the PCI Hot Plug Controller is ready to accept
another command; it does not ensure that the previous command is completely finished. A
Hot Plug controller command is defined as a state change in any of the *_CTL bits in the Slot
4 CC ruc
Control register (i.e., software writes).
0 – PCI Hot Plug controller is not ready to accept a new command.
1 – PCI Hot Plug controller is ready to accept a new command.
Presence detect changed. This bit indicates whether the state of the PDS bit has changed.
3 PDC ruc 0 – PDS bit has not changed.
1 – PDS bit has changed.
116 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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