Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-81. Bit Descriptions – Slot Control Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Power indicator control. When read, this field indicates the current state of the power indicator.
Writes set the power indicator state. When writes cause this field to change, the appropriate
POWER_INDICATOR_* messages are sent. This bit controls the PWR_LED output pin.
00b – Reserved
9:8 PI_CTL rw
01b – On
10b – Blinking
11b – Off
Attention indicator control. When read, this field indicates the current state of the attention
indicator. Writes set the attention indicator state. When writes cause this field to change, the
appropriate ATTENTION_INDICATOR_* messages are sent. This bit controls the ATN_LED
output pin.
7:6 AI_CTL rw
00b – Reserved
01b – On
10b – Blinking
11b – Off
PCI Hot Plug interrupt enable. This bit enables generation of PCI Hot Plug interrupts on enabled
PCI Hot Plug events.
5 HPI_EN rw
0 – PCI Hot Plug interrupts disabled
1 – PCI Hot Plug interrupts enabled
Command-completed interrupt enable. This bit enables generation of an interrupt upon completion
of a command by the PCI Hot Plug Controller. HPI_EN, and MSI_EN (see MSI Message Control
register) must also be enabled for interrupt generation. A Hot Plug Controller Command is defined
4 CCI_EN rw
as a state change in any of the *_CTL bits in this register (i.e., software writes).
0 – Command-completed interrupts disabled
1 – Command-completed interrupts enabled
Presence detect changed enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the PDC bit in the Slot Status register is asserted.
3 PDC_EN rw
0 – Disabled
1 – Enabled
HPI_EN and MSI_EN (see MSI Message Control register) must also be enabled for interrupt
generation. PME_EN must also be enabled for PME signaling during D1, D2, or D3hot. For more
information, see section 6.7.7 in PCI Express Base Specification Revision 1.0a.
Manual retention latch sensor changed enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the MRLSC bit in the Slot Status register is asserted.
2 MRLSC_EN rw
0 – Disabled
1 – Enabled
HPI_EN and MSI_EN (see MSI Message Control register) must also be enabled for interrupt
generation. PME_EN must also be enabled for PME signaling during D1, D2, or D3hot. For more
information, see section 6.7.7 in PCI Express Base Specification Revision 1.0a.
Power fault detected enable. This bit enables generation of a
•＝＝＝＝＝＝＝＝＝ PCI Hot Plug interrupt
•＝＝＝＝＝＝＝＝＝ PME
when the PFD bit in the Slot Status register is asserted.
1 PFD_EN rw
0 – Disabled
1 – Enabled
HPI_EN and MSI_EN (see MSI Message Control register) must also be enabled for interrupt
generation. PME_EN must also be enabled for PME signaling during D1, D2, or D3hot. For more
information, see section 6.7.7 in PCI Express Base Specification Revision 1.0a.
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