Specifications

XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010 www.ti.com
Table 4-80. Bit Descriptions – Slot Capabilities Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Manual retention latch sensor present. This bit indicates whether a manual retention latch
(MRL) sensor is implemented on the chassis for this slot. This bit can be programmed by
writing to the General Control register bit 10, which is SLOT_MRLSP. For more information
2 MRLSP r
on the General Control register, see section 3.3.61.
0 – MRL sensor not present
1 – MRL sensor present
Power controller present. This bit indicates whether a power controller is implemented for
this slot. The default setting of this register is defined by the DPSTRP[2,0] strapping. This bit
can be programmed by writing to the General Control register bit 9, which is SLOT_PCP. For
more information on the General Control Register, see section 3.3.61. If this bit is zero, then
1 PCP r
the PWRON_EC output signal, which may go to a pin, is forced asserted; there is no such
effect on the PWRON output signal.
0 – Power controller not present
1 – Power controller present
Attention button present. This bit indicates whether an attention button is implemented on the
chassis for this slot. This bit can be programmed by writing to the General Control register bit
8, which is SLOT_ABP. For more information on the General Control register, see section
0 ABP r
3.3.61.
0 – Attention button not present
1 – Attention button present
4.3.56 Slot Control Register
The Slot Control register controls slot-specific parameters.
PCI register offset: A8h
Register type: Read/Write; Read Only
Default value: 07C0h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0
Table 4-81. Bit Descriptions – Slot Control Register
BIT FIELD NAME ACCESS DESCRIPTION
15:13 RSVD r Reserved. When read, these bits return zeros.
Data link layer state changed enable. This bit enables software notification (i.e., interrupts) due to
an assertion of the DLLSC field in the Slot Status register.
12 DLLSC_EN rw
0 – DLLSC interrupts disabled
1 – DLLSC interrupts enabled
Electromechanical interlock control. When read, this bit returns zero. A write of 1’b0 has no effect.
11 EMIL_CTL rw If the EMILP field in the Slot Capabilities register is asserted, then a write of 1’b1 causes a 100 ms
high-going pulse on the EMIL_CTL output pin; otherwise, the write has no effect.
Power controller control. When read, this bit indicates the current state of power applied to the
slot. Writes set the power state of the slot and control the PWR_ON pin. When this bit transitions
from power on to power off, and the HP_PME_MSG_EN bit in the Global Switch Control register
is asserted, a PME_Turn_Off message is sent and the PWRON output pin gets de-asserted only
10 PC_CTL rw
after a PME_TO_Ack is received or after a 100 ms timeout.
0 – Power on
1 – Power off
114 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): XIO3130