Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Table 4-80. Bit Descriptions – Slot Capabilities Register
BIT FIELD NAME ACCESS DESCRIPTION
Physical slot number. This field indicates a system-dependent physical slot number that is
31:19 SLOT_NUM r unique to each slot in the system. This field can be programmed by writing to the General
Slot Info register.
Electromechanical interlock present. This bit indicates whether an electromechanical
interlock is implemented on the chassis for this slot. This bit can be programmed by writing
to the General Control register.
18 EMILP ru
0 – Electromechanical interlock not present.
1 – Electromechanical interlock present.
No command completed support. This bit is hardwired to zero, which indicates that
command completed software notification (i.e., interrupt generation) is always supported.
17 NCCS ru
0 – Command completed support is provided.
1 – Command completed support is not provided.
Slot power limit scale. This field Indicates the scale that is used for the slow power limit
value. This field may be written only once after any given PERST; the effect when written is
to cause the port to send the Set_Slot_Power_Limit message.
00 – 1.0x
16:15 SPLS rw
01 – 0.1x
10 – 0.01x
11 – 0.001x
This field is loaded from EEPROM (if present) and reset with PERST.
Slot power limit value. When multiplied by the SPLS field (see previous row in this table), this
field indicates the maximum power in watts that can be consumed by a card plugged into a
slot attached to this port,. This field may be written only once after any given PERST; the
14:7 SPLV rw
effect when written is to cause the port to send the Set_Slot_Power_Limit message.
This field is loaded from EEPROM (if present) and reset with PERST.
PCI Hot Plug capable. This bit indicates whether this slot is capable of supporting PCI Hot
Plug operations. The default setting of this register is defined by the DPSTRP[2,0] strapping.
This bit can be programmed by writing to the General Control register bit 14, which is
6 HP_CAPABLE r
SLOT_HPC. For more information on the General Control register, see section 3.3.61.
0 – Incapable of supporting PCI Hot Plug operations
1 – Capable of supporting PCI Hot Plug operations
PCI Hot Plug surprise. This bit indicates whether a device present in this slot can be
removed from the system without any prior notification. This bit can be programmed by
writing to the General Control register bit 13, which is SLOT_HPS. For more information on
5 HP_SURPRISE r
the General Control register, see section 3.3.61.
0 – No device present that can be removed by surprise
1 – Device present that can be removed by surprise
Power indicator present. This bit indicates whether a power indicator is implemented on the
chassis for this slot. This bit can be programmed by writing to the General Control register bit
12, which is SLOT_PIP. For more information on the General Control register, see section
4 PIP r
3.3.61.
0 – Power indicator not present
1 – Power indicator present
Attention indicator present. This bit indicates whether an attention indicator is implemented
on the chassis for this slot. This bit can be programmed by writing to the General Control
register bit 11, which is SLOT_AIP. For more information on the General Control register,
3 AIP r
see section 3.3.61.
0 – Attention indicator not present
1 – Attention indicator present
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