Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-75. Bit Descriptions – Device Control Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Auxiliary power PM enable. This bit is read-only zero, since the XIO3130 requires a minimal
10 APPE r
amount of AUX power when PME is disabled.
Phantom function enable. Since the XIO3130 part does not support phantom functions, this
9 PFE r
bit is read-only zero.
Extended tag field enable. Since the XIO3130 part does not support extended tags, this bit
8 ETFE r
is read-only zero.
Max payload size. This field is programmed by the host software to set the maximum size of
posted writes or read completions that the XIO3130 can initiate. This field is encoded as:
000 – 128B (default)
001 – 256B
010 – 512B
7:5 MPS rw
011 – 1024B
100 – 2048B
101 – 4096B
110 – Reserved
111 – Reserved
Enable relaxed ordering. Since the XIO3130 part does not support relaxed ordering, this bit
4 ERO r
is read-only zero.
Unsupported request reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when an unsupported request is received
by the downstream port.
3 URRE rw
0 – Do not report unsupported requests to the root complex.
1 – Report unsupported requests to the root complex.
Fatal error reporting enable. If this bit is set, the XIO3130 is enabled to send ERR_FATAL
messages to the root complex when a system error event occurs.
2 FERE rw
0 – Do not report fatal errors to the root complex.
1 – Report fatal errors to the root complex.
Nonfatal error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when a system error event occurs.
1 NFERE rw
0 – Do not report nonfatal errors to the root complex.
1 – Report nonfatal errors to the root complex.
Correctable error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_CORR messages to the root complex when a system error event occurs.
0 CERE rw
0 – Do not report correctable errors to the root complex.
1 – Report correctable errors to the root complex.
4.3.51 Device Status Register
The Device Status register controls PCI Express device-specific parameters.
PCI register offset: 9Ah
Register type: Read Only; Clear by a Write of One; Hardware Update
Default value: 00X0h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0
Copyright © 2007–2010, Texas Instruments Incorporated XIO3130 Configuration Register Space 109
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