Specifications
XIO3130
www.ti.com
SLLS693F–MAY 2007–REVISED JANUARY 2010
4.3.47 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130 downstream port. This register reads 00h, which indicates that no additional capabilities are
supported.
PCI register offset: 91h
Register type: Read only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.3.48 PCI Express Capabilities Register
This register indicates the capabilities of the downstream port of the XIO3130 related to PCI Express.
PCI register offset: 92h
Register type: Read only
Default value: 0061h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1
Table 4-73. Bit Descriptions – PCI Express Capabilities Register
BIT FIELD NAME ACCESS DESCRIPTION
15:14 RSVD r Reserved. When read, these bits return zeros.
Interrupt message number. This field is used for MSI support and is implemented as read-only
13:9 INT_NUM r
zero.
Slot implemented. This bit indicates whether the port is connected to a slot connector (e.g., for
PCI Express, ExpressCard™ or other add-in cards). This field can be programmed by writing to
the General Control register.
8 SLOT r
0 – Port not connected to a slot
1 – Port connected to a slot
Device/Port type. This read-only field returns 0110b, which indicates that the device is a
7:4 DEV_TYPE r
downstream port of a PCI Express XIO3130.
Capability version. This field returns 0001b, which indicates revision 1 of the PCI Express
3:0 VERSION r
capability.
4.3.49 Device Capabilities Register
The Device Capabilities register indicates the device-specific capabilities of the XIO3130 downstream port.
PCI register offset: 94h
Register type: Read Only; Hardware Update
Default value: 0000 8XX1h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 0 u u u v v v 0 0 0 0 0 1
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