Specifications

XIO3130

SLLS693F–MAY 2007 –REVISED JANUARY 2010

www.ti.com

4.3.43 Next-Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the

XIO3130 downstream port. This register reads 90h, which points to the PCI Express Capabilities registers.

PCI register offset: 81h

Default value: 90h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 1 0 0 0 0

4.3.44 Subsystem Vendor ID Register

This register is used for system and option card identification and may be required for certain operating

systems. This read-only register is a direct reflection of the upstream port’s Subsystem Access register,

which is read/write and is initialized through the EEPROM (if present).

PCI register offset: 84h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.3.45 Subsystem ID Register

This register is used for system and option card identification and may be required for certain operating

systems. This read-only register is a direct reflection of the upstream port’s Subsystem Access register,

which is read/write and is initialized through the EEPROM (if present).

PCI register offset: 86h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.3.46 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for PCI Express Capabilities. When

read, this register returns 10h.

PCI register offset: 90h

Default value: 10h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 1 0 0 0 0

Submit Documentation Feedback

Product Folder Link(s): XIO3130