Specifications

XIO3130
www.ti.com SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-67. Bit Descriptions – Power Management Capabilities Register (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Device-specific initialization. This bit returns 0 when read, which indicates that the
5 DSI r XIO3130 does not require special initialization beyond the standard PCI configuration
header before a generic class driver is able to use it.
4 RSVD r Reserved. When read, this bit returns zero.
PME clock. This bit returns zero, which indicates that the PCI clock is not needed to
3 PME_CLK r
generate PME.
Power management version. This field returns 3’b011, which indicates Revision 1.2
2:0 PM_VERSION r
compatibility.
4.3.33 Power Management Control/Status Register
This register determines and changes the current power state of the downstream port.
PCI register offset: 54h
Register type: Read/Write; Read Only; Clear by a Write of One; Hardware Update; Sticky
Default value: 0008h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Table 4-68. Bit Descriptions – Power Management Control/Status Register
BIT FIELD NAME ACCESS DESCRIPTION
PME status. PME events are generated due to PCI Hot Plug events. This bit reflects the
PME status regardless of the state of PME_EN.
0 – No PME event pending
15 PME_STAT rcuh
1 – PME event pending
This bit is reset with GRST.
Data scale. This 2-bit field returns 0s when read since the XIO3130 does not use the Data
14:13 DATA_SCALE r
register.
Data select. This 4-bit field returns 0s when read since the XIO3130 does not use the Data
12:9 DATA_SEL r
register.
PME enable. This bit enables PME/WAKE signaling, even though the XIO3130 never
generates WAKE .
0 – Disable PME signaling.
8 PME_EN rwh
1 – Enable PME signaling.
This bit is reset with GRST.
7:4 RSVD r Reserved. When read, these bits return zeros.
No Soft Reset. This bit controls whether the transition from D3hot to D0 resets the state
according to PCI Power Management Specification Revision 1.2. This bit is hardwired to
1’b1.
3 NO_SOFT_RST r
0 – D3hot to D0 transition causes reset.
1 – D3hot to D0 transition does not cause reset.
2 RSVD r Reserved. When read, this bit returns zero.
Power state. This 2-bit field is used to determine the current power state of the function and
to set the function into a new power state. This field is encoded as follows:
00 = D0
1:0 PWR_STATE rw
01 = D1
10 = D2
11 = D3hot
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