Specifications
XIO3130
SLLS693F–MAY 2007 –REVISED JANUARY 2010
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4.3.30 Capability ID Register
This read-only register identifies the linked list item as the register for PCI power management. It returns
01h when read.
PCI register offset: 50h
Register type: Read only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
4.3.31 Next-Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the
XIO3130 downstream port. This register reads 70h, which points to the MSI Capabilities registers.
PCI register offset: 51h
Register type: Read only
Default value: 70h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 1 1 1 0 0 0 0
4.3.32 Power Management Capabilities Register
This register indicates the capabilities of the XIO3130 downstream port related to PCI power
management.
PCI register offset: 52h
Register type: Read only
Default value: XXX3h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE y 1 1 x 1 1 x 0 0 y 0 0 0 0 1 1
Table 4-67. Bit Descriptions – Power Management Capabilities Register
BIT FIELD NAME ACCESS DESCRIPTION
PME support. This 5-bit field indicates the power states from which the downstream port
may assert PME. These five bits return a value of 5’by11x1, which indicates that the
XIO3130 can assert PME from D0, D2, D3hot, maybe D3cold (i.e., depending on y), and
15:11 PME_SUPPORT r maybe D1 (i.e., depending on x). The bit that defines this power state for D3cold (i.e., y) is
controlled by the AUX_PRESENT bit in the Global Chip Control register. The bit defining
this power state for D1 (i.e., x) is controlled by the D1_SUPPORT bit in the Global Switch
Control register.
This bit returns a 1 when read, which indicates that the function supports the D2 device
10 D2_SUPPORT r
power state.
This bit indicates whether the function supports the D1 device power state. This bit is
controlled by the D1_SUPPORT bit in the Global Switch Control register. The default
9 D1_SUPPORT r
value x is controlled by the default value for the D1_SUPPORT bit in the Global Switch
Control register.
3.3-V
AUX
auxiliary current requirements. This field reads 3’b00y, i.e., either 3’b001 or
3’b000, depending on the AUX_PRESENT bit in the Global Chip Control register. 3’b001
8:6 AUX_CURRENT r
indicates 55 mA maximum current in D3cold when PME is enabled, according to PCI
Power Management Specification Revision 1.2, Section 3.2.3, page 26.
100 XIO3130 Configuration Register Space Copyright © 2007–2010, Texas Instruments Incorporated
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