User`s manual

En-32
MS-7681 Manboard
Intel Turbo Booster
Ths tem wll appear when you nstall a CPU wth Intel Turbo Boost technology. Ths
tem s used to enable/ dsable Intel Turbo Boost technology. It can scale processor
frequency hgher dynamcally when applcatons demand more performance and TDP
headroom exsts. It also can delver seamless power scalablty (Dynamcally scale up,
Speed-Step Down). It s the Intel newly technology wthn newly CPU.
DRAM Rato
Ths settng controls the rato of memory frequency to enable the memory to run at df
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ferent frequency combnatons.
Extreme Memory Prole(X.M.P)
Ths tem s used to enable/dsable the Intel Extreme Memory Prole (XMP). For further
nformaton please refer to Intel’s ocal webste.
Adjusted DRAM Frequency
It shows the adjusted DRAM frequency. Read-only.
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect) EE
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PROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the followng
“Advanced DRAM Conguraton” sub-menu to be determned by BIOS based on the
conguratons on the SPD. Selectng [Lnk] or [Unlnk] allows users to congure the
DRAM tmngs and the followng related “Advanced DRAM Conguraton” sub-menu
manually.
Advanced DRAM Conguraton
Press <Enter> to enter the sub-menu.
Command Rate2
Ths settng controls the DRAM command rate.
tCL
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row ad
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dress strobe) to CAS (column address strobe). The less the clock cycles, the faster
the DRAM performance.
tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsucent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refreshng may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
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