Specifications

80 IBM Flex System p260 and p460 Planning and Implementation Guide
POWER7 processor overview
The POWER7 processor chip is fabricated with the IBM 45 nm
silicon-on-insulator technology, using copper interconnects, and uses an on-chip
L3 cache with eDRAM.
The POWER7 processor chip is 567 mm
2
and is built using 1,200,000,000
components (transistors). Eight processor cores are on the chip, each with 12
execution units, 256 KB of L2 cache, and access to up to 32 MB of shared
on-chip L3 cache.
For memory access, the POWER7 processor includes an integrated Double
Data Rate 3 (DDR3) memory controller, each with four memory channels. To
scale effectively, the POWER7 processor uses a combination of local and global
high-bandwidth SMP links.
Table 4-3 summarizes the technology characteristics of the POWER7 processor.
Table 4-3 Summary of POWER7 processor technology
Technology POWER7 processor
Die size 567 mm
2
Fabrication technology 򐂰 45 nm lithography
򐂰 Copper interconnect
򐂰 Silicon-on-insulator
򐂰 eDRAM
Components 1,200,000,000 components (transistors) offering
the equivalent function of 2,700,000,000 (For more
details, see “On-chip L3 intelligent cache” on
page 85)
Processor cores 4
Max execution threads core/chip 4/32
L2 cache per core/per chip 256 KB / 2 MB
On-chip L3 cache per core per
chip
4 MB / 32 MB
DDR3 memory controllers One per processor
Compatibility Compatible with prior generations of
the POWER processor